Quartus除法器設(shè)計(jì)VHDL代碼

名稱：Quartus除法器設(shè)計(jì)VHDL代碼

軟件：Quartus

語言：VHDL

代碼功能：

位寬可配置的硬件除法器，具體除數(shù)，被除數(shù)輸入，輸出為商和余數(shù)。

除法器位寬可以自定義，修改如下參數(shù)即可：

constant DIVIDEND_WIDTH : natural := 32;

constant DIVISOR_WIDTH : natural := 16;

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計(jì)文檔：

1.工程文件

2.程序文件

3.程序編譯

4.Testebnch

5.仿真圖

部分代碼展示:

library?IEEE;
use?IEEE.std_logic_1164.all;
use?ieee.std_logic_unsigned.all;
use?ieee.numeric_std.all;
--Additional?standard?or?custom?libraries?go?here
--use?work.display_divier.all;
entity?comparator?is
generic(
DATA_WIDTH?:?natural?:=?4
);
port(
--Inputs
DINL?:?in?std_logic_vector?(DATA_WIDTH?downto?0);
DINR?:?in?std_logic_vector?(DATA_WIDTH-1?downto?0);
--Outputs
DOUT?:?out?std_logic_vector?(DATA_WIDTH-1?downto?0);
isGreaterEq?:?out?std_logic
);
end?entity?comparator;
architecture?behavioral?of?comparator?is
--Signals?and?components?go?here
signal?calc?:??std_logic_vector?(DATA_WIDTH-1?downto?0);
begin
--Behavioral?design?goes?here
calc<=?std_logic_vector(resize(unsigned(DINL)-unsigned(DINR),DATA_WIDTH));
Dout?<=?calc?when?(DINL?>=?DINR)?else?DINL(DATA_WIDTH-1?downto?0);
isGreaterEq?<=?'1'?when?(DINL?>=?DINR)?else?'0';
end?architecture?behavioral;

點(diǎn)擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=406