Quartus智能函數(shù)發(fā)生器VHDL代碼

名稱：Quartus智能函數(shù)發(fā)生器VHDL代碼

軟件：Quartus

語言：VHDL

代碼功能：

設(shè)計一個智能函數(shù)發(fā)生器,能夠以穩(wěn)定的頻率產(chǎn)生遞增斜波、遞減斜波、三角波、梯形波、正弦波和方波。設(shè)置一個波形選擇開關(guān),通過此開關(guān)可以選擇以上各種不同種類的輸出函數(shù)波形。系統(tǒng)具備復(fù)位功能。

總結(jié)報告要求

1、完整的設(shè)計任務(wù)書。

2、設(shè)計摘要、目錄與緒論。

3、系統(tǒng)方案設(shè)計。

4、器件選型與系統(tǒng)硬件設(shè)計。

5、模塊、系統(tǒng)VHDL代碼設(shè)計。

6、系統(tǒng)調(diào)試方案、調(diào)試結(jié)果及注意事項7、設(shè)計體會。

8、參考文獻(xiàn)等。

9、2#手繪系統(tǒng)硬件電路圖、系統(tǒng)建模圖和關(guān)鍵模塊狀態(tài)轉(zhuǎn)換圖。

三、設(shè)計進(jìn)度

第1周:系統(tǒng)設(shè)計方案確定;系統(tǒng)建模設(shè)計,關(guān)鍵模塊端口、時序設(shè)計,元器件選型以及硬件電路設(shè)計。

第2周:模塊代碼設(shè)計、仿真測試,控制器代碼設(shè)計、仿真測試,控制系統(tǒng)調(diào)試。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計文檔：

波形發(fā)生器原理

1. 工程文件

2. 程序文件

ROM IP核

3. 程序編譯

4. RTL圖

5. Testbench

6. 仿真圖

整體仿真圖

相位累加器模塊

波形選擇模塊

正弦波ROM

三角波ROM

方波ROM

遞增斜波ROM

遞減斜波ROM

梯形波ROM

部分代碼展示:

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
--信號發(fā)生器
ENTITY?DDS_top?IS
???PORT?(
??????clk_50M??????:?IN?STD_LOGIC;--時鐘
rst_n????????:?IN?STD_LOGIC;--復(fù)位
??????wave_select??:?IN?STD_LOGIC_VECTOR(2?DOWNTO?0);--波形選擇開關(guān)：001輸出sin，010輸出方波，011輸出三角波,100輸出遞增斜波,101輸出遞減斜波,110輸出梯形波
??????wave?????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)--輸出波形
???);
END?DDS_top;
ARCHITECTURE?behave?OF?DDS_top?IS
--例化模塊
???COMPONENT?wave_sel?IS
??????PORT?(
?????????clk_50M??????:?IN?STD_LOGIC;
rst_n????????:?IN?STD_LOGIC;--復(fù)位
?????????wave_select??:?IN?STD_LOGIC_VECTOR(2?DOWNTO?0);--001輸出sin，010輸出方波，011輸出三角波,100輸出遞增斜波,101輸出遞減斜波,110輸出梯形波
?????????douta_fangbo?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????douta_sanjiao?:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????douta_sin????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????douta_add????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--遞增波
?????????douta_sub????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--遞減波
?????????douta_trap???:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);--梯形波
?????????wave?????????:?OUT?STD_LOGIC_VECTOR(7?DOWNTO?0)
??????);
???END?COMPONENT;
???
???COMPONENT?Frequency_ctrl?IS
??????PORT?(
?????????clk_50M??????:?IN?STD_LOGIC;
?????????frequency????:?IN?STD_LOGIC_VECTOR(7?DOWNTO?0);
?????????addra????????:?OUT?STD_LOGIC_VECTOR(9?DOWNTO?0)
??????);
???END?COMPONENT;
COMPONENT?sin_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
COMPONENT?fangbo_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
COMPONENT?sanjiao_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
COMPONENT?sub_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
COMPONENT?add_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
???
COMPONENT?trap_ROM?IS
PORT
(
address:?IN?STD_LOGIC_VECTOR?(9?DOWNTO?0);
clock:?IN?STD_LOGIC??:=?'1';
q:?OUT?STD_LOGIC_VECTOR?(7?DOWNTO?0)
);
END?COMPONENT;
???SIGNAL?addra?????????:?STD_LOGIC_VECTOR(9?DOWNTO?0);
???SIGNAL?douta_fangbo??:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?douta_sanjiao?:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?douta_sin?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?douta_add?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?douta_sub?????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
???SIGNAL?douta_trap????:?STD_LOGIC_VECTOR(7?DOWNTO?0);
BEGIN
???
???--方波ROM
???i_fangbo_ROM?:?fangbo_ROM
??????PORT?MAP?(
?????????clock???=>?clk_50M,
?????????address??=>?addra,
?????????q??=>?douta_fangbo
??????);
???
???
???--三角波ROM
???i_sanjiao_ROM?:?sanjiao_ROM
??????PORT?MAP?(
?????????clock???=>?clk_50M,
?????????address??=>?addra,
?????????q??=>?douta_sanjiao
??????);
???
???
???--sin波ROM
???i_sin_ROM?:?sin_ROM
??????PORT?MAP?(
?????????clock???=>?clk_50M,
?????????address??=>?addra,
?????????q??=>?douta_sin
??????);
???--add波ROM--遞增斜波
???i_add_ROM?:?add_ROM
??????PORT?MAP?(
?????????clock???=>?clk_50M,
?????????address??=>?addra,
?????????q??=>?douta_add
??????);
???--sub波ROM--遞減斜波
???i_sub_ROM?:?sub_ROM
??????PORT?MAP?(
?????????clock???=>?clk_50M,
?????????address??=>?addra,
?????????q??=>?douta_sub
??????);
???--梯形波ROM
???i_trap_ROM?:?trap_ROM
??????PORT?MAP?(
?????????clock???=>?clk_50M,
?????????address??=>?addra,
?????????q??=>?douta_trap
??????);
???
???--相位累加器
???i_Frequency_ctrl?:?Frequency_ctrl
??????PORT?MAP?(
?????????clk_50M????=>?clk_50M,
?????????frequency??=>?"00000001",--頻率控制字
?????????addra??????=>?addra--輸出地址
??????);
???
???
???--波形選擇控制
???i_wave_sel?:?wave_sel
??????PORT?MAP?(
?????????clk_50M????????=>?clk_50M,
rst_n??????????=>?rst_n,--復(fù)位
?????????wave_select????=>?wave_select,----001輸出sin，010輸出方波，011輸出三角波,100輸出遞增斜波,101輸出遞減斜波,110輸出梯形波
?????????douta_fangbo???=>?douta_fangbo,--方波
?????????douta_sanjiao??=>?douta_sanjiao,--三角
?????????douta_sin??????=>?douta_sin,--正弦
?????????douta_add??????=>?douta_add,--遞增波
?????????douta_sub??????=>?douta_sub,--遞減波
?????????douta_trap?????=>?douta_trap,--梯形波
?????????wave???????????=>?wave--輸出波形?
??????);
???
END?behave;

點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=386