Quartus濾波器系數(shù)設(shè)計verilog代碼

名稱：Quartus濾波器系數(shù)設(shè)計verilog代碼

軟件：Quartus

語言：Verilog

代碼功能：

濾波器系數(shù)設(shè)計:打開Matlab軟件在指令窗口中鍵入:m=fir1(7,0.2)，即可得到如下的系數(shù):

0.009、0.048、0.164、0.279、0.279、0.164、0.048、0.009

將系數(shù)放大1000倍即：9,48,164,279;乘加計算計算完成后再除以1000。

濾波器截止頻率為20KHz。

FPGA代碼Verilog/VHDL代碼資源下載：www.hdlcode.com

演示視頻：

設(shè)計文檔：

1. 工程文件

2. 程序文件

3. 程序編譯

4. RTL圖

5. Testbench

6. 仿真圖

部分代碼展示:

//8階線性相位結(jié)構(gòu)FIR
module?FIR(
input?clk,//100K
input?reset_p,//高電平復(fù)位
input??[9:0]data_in,//周期1K，噪聲頻率20K左右
output?[9:0]fir_data//濾波后結(jié)果
);
wire?[31:0]?mul_data_1;
wire?[31:0]?mul_data_2;
wire?[31:0]?mul_data_3;
wire?[31:0]?mul_data_4;
wire?[31:0]add_data;
reg??[9:0]?shift_data_0=10'd0;
reg??[9:0]?shift_data_1=10'd0;
reg??[9:0]?shift_data_2=10'd0;
reg??[9:0]?shift_data_3=10'd0;
reg??[9:0]?shift_data_4=10'd0;
reg??[9:0]?shift_data_5=10'd0;
reg??[9:0]?shift_data_6=10'd0;
reg??[9:0]?shift_data_7=10'd0;
//濾波器系數(shù)設(shè)計:打開Matlab軟件在指令窗口中鍵入:m=fir1(7,0.2)，即可得到如下的系數(shù):
//0.009、0.048、0.164、0.279、0.279、0.164、0.048、0.009
//將系數(shù)放大1000倍即：9,48,164,279;乘加計算計算完成后再除以1000.
//乘加計算
assign?mul_data_1=9*(shift_data_0+shift_data_7);//線性結(jié)構(gòu)，對稱結(jié)構(gòu)
assign?mul_data_2=48*(shift_data_1+shift_data_6);
assign?mul_data_3=164*(shift_data_2+shift_data_5);
assign?mul_data_4=279*(shift_data_3+shift_data_4);?
assign?add_data=(mul_data_1+mul_data_2+mul_data_3+mul_data_4)/1000;//累加，再除以1000.
assign?fir_data=add_data[9:0];//濾波后結(jié)果
//移位寄存器，每個時鐘移位一次
always?@(posedge?clk?or?posedge?reset_p)
????begin
????????if(reset_p)
????????begin
????????????shift_data_0<=10'd0;
????????????shift_data_1<=10'd0;
????????????shift_data_2<=10'd0;
????????????shift_data_3<=10'd0;
????????????shift_data_4<=10'd0;
????????????shift_data_5<=10'd0;
????????????shift_data_6<=10'd0;
????????????shift_data_7<=10'd0;
????????end
????????else
????????begin
shift_data_0<=data_in;
????????????shift_data_1<=shift_data_0;
????????????shift_data_2<=shift_data_1;
????????????shift_data_3<=shift_data_2;
????????????shift_data_4<=shift_data_3;
????????????shift_data_5<=shift_data_4;
????????????shift_data_6<=shift_data_5;
????????????shift_data_7<=shift_data_6;
????????end
????end
endmodule

點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=409